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block diagram 3-phase ac motor controller ic features ? floating channel up to +1200v ? soft over-current shutdown turns off output ? integrated desaturation circuit ? two stage turn on output for di/dt control ? integrated brake igbt driver with protection ? voltage feedback sensing function ? separate pull-up/pull-down output drive pins ? matched delay outputs ? under voltage lockout with hysteresis band ? programmable deadtime ? hard shutdown function product summary v offset 1200v max. i o +/- (min.) 220ma/460ma v out 12.5v - 20v brake (io+/- min) 40ma/80ma deadtime asymmetry skew (max.) 145nsec deadtime (typ. with rdt=39k ? ) 1 sec desat blanking time (typ.) 3.0 sec dsh, dsl input voltage threshold (typ.) 8.0v soft shutdown duration time (typ.) 6.0 sec voltage feedback matching delay time (max.) 125nsec www.irf.com 1 description the ir2238q is a high voltage, 3-phase igbt driver best suited for ac motor drive applications. integrated desaturation logic provides all mode of overcurrent protection, including ground fault protection. soft shut- down is predominantly initiated in the event of overcurrent followed by turn-off of all six outputsf. a shutdown input is provided for a customized shut- down function. the dt pin allows external resistor to program the deadtime. output drivers have separate turn on/off pins with two stage turn-on output to achieve the desired di/dt switching level of igbt. voltage feedback provides accurate volts *seconds measurement. ir2238q data sheet no. pd60228 (refer to lead assignments for correct pin configuration). this diagram shows electrical connections only. package 64-lead mqfp hop1,2,3 hon1,2,3 lop1,2,3 lon1,2,3 br vs1,2,3 vb1,2,3 com lin1,2,3 hin1,2,3 fault vfh1,2,3 vcc vss brin dsh1,2,3 3 up,control 15v dc bus ir2238q u v w motor 3 vfl1,2,3 dsl1,2,3 vcc sd vcc dsb loq1,2,3 hoq1,2,3 dt
2 www.irf.com ir2238q absolute maximum ratings (tentative) absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage parameters are absolute voltages referenced to com, all currents are defined positive into any lead. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. symbol definition min. max. units v s high side offset voltage v b1,2,3 -25 v b1,2,3 +0.3 v b high side floating supply voltage -0.3 1225 v ho high side floating output voltage (hop, hon, hoq) v s1,2,3 - 0.3 v b1,2,3 + 0.3 v cc low side and logic fixed supply voltage -0.3 25 v ss logic ground v cc - 25 v cc + 0.3 v lo low side output voltage (lop, lon, loq) -0.3 v cc + 0.3 v in logic input voltage ( hin/n,lin, brin/n, sd )v ss - 0.3 v cc + 0.3 or v ss + 15 which ever is lower v flt fault output voltage v ss - 0.3 v cc + 0.3 v f feedback output voltage v ss - 0.3 v cc + 0.3 v dsh high side desat/feedback input voltage v s1,2,3 - 0.3 v b1,2,3 + 0.3 v dsl low side desat/feedback input voltage - 0.3 v cc + 0.3 v br brake output voltage -0.3 v cc + 0.3 dvs/dt allowable offset voltage slew rate ? 50 v/ns p d package power dissipation @ t a +25 c ? 2.0 w rth ja thermal resistance, junction to ambient ? 60 t j junction temperature ? 125 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) ? 300 c/w v c recommended operating conditions for proper operation the device should be used within the recommended conditions. all voltage parameters are absolute voltages referenced to com. the v s offset rating is tested with all supplies biased at 15v differential. v b1,2,3 high side floating supply voltage v s1,2,3 + 13 v s1,2,3 + 20 v s1,2,3 high side floating supply offset voltage note 1 1200 v ho1,2,3 high side (hop/hoq/hon) output voltage v s1,2,3 v b1,2,3 v lo1,2,3 low side (lop/loq/lon) output voltage v com v cc v in logic input voltage ( hin/n,lin,brin/n sd )v ss v ss + 5 v cc low side supply voltage 12.5 20 v ss logic ground -5 +5 v flt fault output voltage v ss v cc v f feedback output voltage v ss v cc v dsh high side desat/feedback input voltage v s1,2,3 - 0.3 v b1,2,3 v dsl low side desat/feedback input voltage - 0.3 v cc v br brake output voltage v com v cc t a ambient temperature -20 115 c symbol definition min. max. units v note 1: logic operational for vs of com-5v to com+1200v. logic state held for vs of com-5v to com-v bs .
www.irf.com 3 ir2238q static electrical characteristics v bias (v cc , v bs 1,2,3) = 15v and t a = 25 o c unless otherwise specified. the v in , v th and i in parameters are refer- enced to v ss and are applicable to all six channels (hop/hoq/hon1,2,3 and lop/loq/lon1,2,3). the v o and i o parameters are referenced to com and v s 1,2,3 and are applicable to the respective output leads: h o1,2,3 and l o1,2,3. v desat and i desat parameters are referenced to com and v s1,2,3 symbol definition min. typ. max. units test conditions v ccuv+ v cc1 supply undervoltage positive going threshold 10.3 11.2 12.5 v ccuv- v cc1 supply undervoltage negative going threshold 9.5 10.2 11.3 v ccuvh v cc1 supply undervoltage lockout hysteresis ? 1.0 ? v bsuv+ v bs supply undervoltage positive going threshold 10.3 11.2 12.5 v bsuv- v bs supply undervoltage negative going threshold 9.5 10.2 11.3 v bsuvh v bs supply undervoltage lockout hysteresis ? 1.0 ? i lk offset supply leakage current ? ? 50 i qbs quiescent v bs supply current ? 150 250 i qcc quiescent v cc supply current ? 3 6 ma v lin =0v, v hin =5v dt = 1 sec v ih logic ?0? input voltage (hin/n, brin/n) (out=lo) 2.0 ? ? v il logic ?1? input voltage (hin/n, brin/n) (out=hi) ? ? 0.8 v t + logic input positive going threshold 1.2 1.6 2.0 (hin/n, lin, brin/n, sd) v t - logic input negative going threshold 0.8 1.2 1.6 (hin/n, lin, brin/n, sd) v t logic input hysteresis (hin, lin, brin, sd) ? 0.4 ? v oh high level output voltage, v bias - v o (normal switching) ? ? 100 hop, hoq, lop, loq v ol low level output voltage, v o (normal switching) ? ? 100 hon, lon i in+ logic ?1? input bias current (hin/n, brin/n) ? 5 ? v in = 0v logic ?1? input bias current (lin, sd) ? 70 ? v in = 5v i in- logic ?0? input bias current (hin/n, brin/n) ? 70 ? v in = 5v logic ?0? input bias current (lin, sd) ? 5 ? v in = 0v i ds+ high dsh, dsl, dsb input bias current ? 15 ? v desat = 15v i ds- low dsh, dsl, dsb input bias current ? 0.1 ? v desat = 0v i o 1 + output high first stage short circuit pulsed current 220 350 ? v o = 0v, v in = 0v pw 200 ns i o 2 + output high second stage short circuit pulsed current 120 200 ? v o = 0v, v in = 0v pw 10 s i o- output low short circuit pulsed current 460 540 ? v o = 15v, v in = 5v pw 10 s v v b1,2,3 = v s1,2,3 = 1200v v lin =0v, v hin =5v v v cc = 12.5 to 20v a io = 1ma mv a ma
4 www.irf.com ir2238q i obr+ br output high short circuit pulsed current 40 70 ? v br =0v, v brin =0v pw 10 s i obr- br output low short circuit pulsed current 80 125 ? v br =15v,v brin =5v pw 10 s v ohb br high level output voltage, v cc -v br ? ? 300 v olb br low level output voltage, v br ? ? 150 v olvf vfh or vfl low level output voltage ? ? 0.8 v i vf = 10ma r on,vf vfh or vfl output on resistance ? 60 ? r on,ss soft shutdown on resistance ? 500 ? r on,flt fault low on resistance ? 60 ? v desat+ high dsh1,2,3 and dsl1,2,3 and dsb input ? 8.0 ? threshold voltage v desat- low dsh1,2,3 and dsl1,2,3 or dsb input ? 7.0 ? threshold voltage v dsth ds input voltage hysteresis ? 1.0 ? symbol definition min. typ. max. units t est conditions mv i br = 1ma ma static electrical characteristics cont. v bias (v cc , v bs 1,2,3) = 15v and t a = 25 o c unless otherwise specified. the v in , v th and i in parameters are refer- enced to v ss and are applicable to all six channels (hop/hoq/hon1,2,3 and lop/loq/lon1,2,3). the v o and i o parameters are referenced to com and v s 1,2,3 and are applicable to the respective output leads: h o1,2,3 and l o1,2,3. v desat and i desat parameters are referenced to com and v s1,2,3 v ac electrical characteristics v bias (v cc, v bs ) = 15v, v s1,2,3 = v ss , t a = 25 o c and c l = 1000 pf unless otherwise specified. symbol definition min. typ. max. units test conditions t on1 turn-on first stage duration time ? 200 ? v in = 0 & 5v rl(hoq/loq) = 10 t on turn-on propagation delay 250 550 750 t off turn-off propagation delay 250 550 750 t r turn-on rise time ? 80 ? t f turn-off fall time ? 25 ? t desat1 dsh to ho soft shutdown propogation delay at ? 3000 ? ho turn-on t desat2 dsh to ho soft shutdown propogation delay after 1000 ? ? blanking t desat3 dsl to lo soft shutdown propogation delay at ? 3000 ? v lin = 5v, lo turn-on v desat =15v, fig.7 v in = 0 & 5v v s1,2,3 = 0 to1200v hop=hon,lop=lon figure 5 propagation delay characteristics ns v hin = 0v, v desat = 15v, figure 7
www.irf.com 5 ir2238q ac electrical characteristics cont. v bias (v cc, v bs ) = 15v, v s1,2,3 = v ss , t a = 25 o c and c l = 1000 pf unless otherwise specified. symbol definition min. typ. max. units test conditions t desat4 dsl to lo soft shutdown propogation delay after 1000 ? ? blanking t desat5 dsb to ho hard shutdown propogation delay ? 1300 ? v hin = 0v, v desat =15v, fig. 7 t desat6 dsb to lo hard shutdown propogation delay ? 1300 ? v lin = 5v, v desat =15v, fig. 7 t desat7 dsb to br hard shutdown propogation delay 1000 ? ? v vbrin = 0v, v dsb =15v, fig. 7 t vfhl1,2,3 vfh high to low propagation delay ? 550 ? v desat =15v to 0v figure 8 t vfhhl1,2,3 vfh low to high pr opagation delay ? 550 ? v desat =0v to 15v figure 8 t vflh1,2,3 vfl low to high pr opagation delay ? 550 ? v desat =0v to 15v figure 8 t vfll1,2,3 vfl high to low pr opagation delay ? 550 ? v desat =15v to 0v figure 8 t pwvf minimum pulse width of vfh and vfl ? 400 ? v desat =15v to 0v or 0v to 15v fig. 8 t ds soft shutdown minimum pulse width of dsx 1000 ? ? t ss soft shutdown duration period ? 6000 ? t flt,desat1 dsh to fault propagation delay at ho turn-on ? 3300 ? t flt,desat2 dsh to fault propagation delay after blanking ? 1300 ? t flt,desat3 dsl to fault propagation delay at lo turn-on ? 3300 ? t flt,desat4 dsl to fault propagation delay after bl anking ? 1000 ? t fltdsb dsb to fault pr opagation delay ? 1000 ? b rin = 0v, v desat =15v, fig. 7 t fltclr lin1 =lin2 =lin3 =0 to fault 9.0 ? ? v desat =15v, fig. 7 t fault minimum fault duration period 9.0 15.0 21.0 v desat =15v, fig. 11 fltclr pending t bl ds blanking time at turn-on ? 3000 ? v in = on, v desat =15v, fig. 7 t sd sd to output shutdown propagation delay ? 600 900 v in = on, v desat =0v, fig. 10 ns propagation delay characteristics v lin = 5v, v desat =15v, fig. 7 c l =1000pf, v ds =15v figure 6 v hin = 0v, v ds =15v, fig. 7 s v lin = 5v, v ds =15v, fig. 7
6 www.irf.com ir2238q ac electrical characteristics cont. v bias (v cc, v bs ) = 15v, v s1,2,3 = v ss , t a = 25 o c and c l = 1000 pf unless otherwise specified. symbol definition min. typ. max. units test conditions t en sd negation to output enable propagation delay ? 600 900 v in =on v desat =0v, fig.10 t onbr br output turn-on propagation ? 110 200 t offbr br output turn-off propagation ? 80 150 t rbr br output turn-on rise time ? 235 400 t fbr br output turn-off fall time ? 130 200 dt deadtime 900 1050 1200 figure 8 external resistor=39k 76 100 124 figure 8 external resistor=0k 4500 5000 5500 figure 8 external resistor=220k mdt deadtime asymmetry skew, any of ? ? 145 dt=1000nsec. dtloff1,2,3-dthoff1,2,3 fig.8 pm pwm propagation delay matchi ng max {ton/to ff} ? ? 125 dt=1000nsec. - min {ton/toff}, (ton/toff are applicable to all six fig.5 channels) vm voltage feedback delay matching, i any of ? ? 125 input pulse width t vfhl1,2,3, t vfhh1,2,3, t vfll1,2,3, t vflh1,2,3 >400 nsec - any of t vfhl1,2,3, t vfhh1,2,3, t vfll1,2,3, figure 9 t vflh1,2,3 i ns ns figure 5 propagation delay characteristics deadtime/delay matching characteristics
www.irf.com 7 ir2238q functional block diagram figure 1 schmitt trigger input & shoot through prevention fault logic schmitt trigger input & shoot through prevention schmitt trigger input & shoot through prevention 100nsec minimum deadtime 100nsec minimum deadtime 100nsec minimum deadtime level shifters level shifters level shifters latch local desat protection soft shutdown voltage feedback uv detect uv detect hin1 hin2 hin3 shutdown fault hin1 lin1 hin2 lin2 hin3 lin3 lop1 lon1 lon2 lop2 lop3 lon3 com driver driver driver driver driver driver hop3 hon3 vs3 vb3 vb2 hop2 hon2 vs2 vb1 hop1 hon1 vs1 vcc vss dsl1 dsl2 dsl3 dsh1 vfb latch local desat protection soft shutdown voltage feedback uv detect latch local desat protection soft shutdown voltage feedback uv detect dsh2 dsh3 soft shutdown di/dt control vfb shutdown shutdown vfb hin1 hin2 hin3 di/dt control di/dt control di/dt control di/dt control di/dt control local desat protection soft shutdown voltage feedback local desat protection soft shutdown voltage feedback local desat protection soft shutdown voltage feedback lin1 lin2 lin3 vfh3 vfh2 vfh1 vfl1 vfl2 vfl3 brake driver br hoq1 hoq2 hoq3 loq1 lop2 loq3 desat detection dsb shutdown clear logic to low side logic brin dt sd
8 www.irf.com ir2238q figure 3 fault logic diagram schmitt trigger input & shoot through prevention 100nsec deadtime level shifters latch local desat protection soft shutdown voltage feedback uv detect uv detect hin1 shutdown fault hin1 lin1 lop1 lon1 com driver driver vb1 hop1 hon1 vs1 vcc vss dsl1 dsh1 vfb shutdown oneshot di/dt control hin1 di/dt control local desat protection soft shutdown voltage feedback lin1 vfh1 vfl1 brake driver br hoq1 loq1 desat detection voltage feedback dsb clear logic to low side logic brin input latch s q q r set clr soft shutdown hard shutdown lin2 lin3 lin2 shutdown oneshot lin3 shutdown oneshot hin3 shutdown oneshot hin2 shutdown oneshot hard shutdown hold latch oneshot 6us fault logic hold fltduration oneshot 12us figure 2 driver output circuit block diagram pre driver 3usec blanking vb hon dsh vs soft shutdown impedence = 500 ohms shutdown hop gate 6usec one shot 8v one shot gate drive circuit block diagram voltage feedback 1usec filter hoq uv detect
www.irf.com 9 ir2238q figure 4 input/output timing diagram hin1,2,3 lin1,2,3 ds/vfl1,2,3 fault dsb ho(hop/hoq/hon) lo(lop/hoq/lon) ds/vfh1,2,3 brin br sd vfl1,2,3 vfh1,2,3
10 www.irf.com ir2238q hin lin ho (hop=hon) lo (lop=lon) t on t r 50% 90% 10% 50% 90% 10% t off t f brin br 5v or 3.3v pw in pw out hoq loq 50% 10% 50% t on1 figure 5 switching time waveforms figure 6.1 low side desat soft shutdown timing waveform lin 1,2,3 lo 1,2,3 8v 7v t ss t desat4 3.3v or 5v dsl t ds soft shutdown driver enable for all l.s. output & hold driver enable for all h.s. output hard shutdown driver enable for all output active lin 1,2,3 lo 1,2,3 8v 7v t ss t desat4 3.3v or 5v dsl t ds soft shutdown driver enable for all l.s. output & hold driver enable for all h.s. output hard shutdown driver enable for all output active
www.irf.com 11 ir2238q figure 6.2 high side desat soft shutdown timing waveform figure 6.3 brake desat timing waveform hin 1 ho 1 8v 7v t ss t desat2 3.3v or 5v dsh 1 t ds soft shutdown driver enable for h.s. output on desaturation and all low side output & hold driver enable for the remaining h.s. output hard shutdown driver enable for all output active active brin br 8v 7v 3.3v or 5v dsb t ds ho 1,2,3 lo 1,2,3 hard shutdown in effect hard shutdown in effect t desat5, t desat6 t desat7 brin br 8v 7v 3.3v or 5v dsb t ds ho 1,2,3 lo 1,2,3 hard shutdown in effect hard shutdown in effect t desat5, t desat6 t desat7
12 www.irf.com ir2238q figure 7 desat timing diagram hin1,2,3 lin1,2,3 dsb fault ho (hop/hoq/hon) lo (lop/loq/lon) t desat1 t desat2 t flt,desat2 t flt,desat1 soft shutdown soft shutdown 8v 50% 90% 50% 50% 50% 90% 8v t bl t bl blanking in effect blanking in effect dsl 8v dsh 8v 8v t desat3 soft shutdown 90% 50% t bl t flt,desat3 50% blanking in effect blanking in effect t bl t desat4 90% soft shutdown t flt,desat4 50% t desat5 90% hard shutdown 8v desat6 90% t t fltclr t fltclr t fltclr t fltclr t fltclr t fltclr 50% 50% t flt,dsb t flt,dsb 50% t desat7 90% t desat7 90% br tfault
www.irf.com 13 ir2238q hin lin ho (hop=hoq=hon) lo (lop=loq=lon) dt dt 90% 10% 90% 10% 50% 50% dtloff 50% 50% dthoff figure 8 internal deadtime timing figure 9 voltage feedback timing dsh1,2,3 vfh1,2,3 10% 10% 90% 90% dsl1,2,3 vfl1,2,3 7v 7v 8v 8v t vfhl1,2,3 t vflh1,2,3 t vfhh1,2,3 t vfll1,2,3 vcc vcc vss vss vb1,2,3 vs1,2,3 vb1,2,3 vs1,2,3
14 www.irf.com ir2238q figure 10 shutdown timing t sd 50% 50% t en sd 5v or 3.3v ho (hop=hoq=hon) lo (lop=lon=loq) 15v 10% 90% figure 11 fault duration with pending faultclear waveform (refer to note ld2 under the lead definition table) lin hin ho dsh fault tfault 50% 50%
www.irf.com 15 ir2238q lead definitions symbol description v cc low side supply voltage vss logic ground hin1,2,3 logic inputs for high side gate driver outputs (hop1,2,3/hon1,2,3, out of phase) lin1,2,3 logic inputs for low side gate driver outputs (lop1,2,3/lon1,2,3, out of phase) fault fault output (latched and open drain) sd shutdown input dt deadtime programmable resistor pin dsb brake igbt desaturation protection input and voltage feedback input brin logic input for brake driver br brake driver output com low side drivers return v b 1,2,3 high side gate drive floating supply hop1,2,3 high side driver sourcing output hoq1,2,3 high side driver boost sourcing output hon1,2,3 high side driver sinking output dsh1,2,3 igbt desaturation protection input and high side voltage feedback input v s1,2,3 high voltage floating supply return lop1,2,3 low side driver sourcing output lon1,2,3 low side driver sinking output dsl1,2,3 igbt desaturation protection input and low side voltage feedback input vfh1,2,3 high side voltage feedback logic output vfl1,2,3 low side voltage feedback logic output note: ld1- low side soft shutdown is initiated locally in an event over current, which is sensed by the dsl pin. it is followed by the synchronized soft shutdown of the rest of the low side outputs; meanwhile it will hold all input information for a period of tss until the soft shutdown finishes. then the hard shutdown will be initiated to complete the shut down cycle. (figure 6.1) high side soft shutdown is initiated locally in an event over current, which is sensed by the dsh pin. it is followed by the synchronized soft shutdown of all the low side outputs; meanwhile it will hold all input information for a period of tss until the soft shutdown finishes. then the hard shutdown will be initiated to complete the shut down cycle. (figure 6.2) ld2- soft shut down is initiated in an event of overcurrent, which is followed by turn-off all six outputs. the fault condition will remain in a fixed period(tfault) even though the faultclear condition is in effect (fig11). in the case that faultclear is not in effect, fault duration = tfault + tfltclr.
16 www.irf.com ir2238q lead assignments 64 lead mqfp ir2238 dt vb1 hop1 hon1 dsh1 vs1 vb2 hop2 hon2 dsh2 vs2 vb3 hop3 hon3 dsh3 vs3 hin1 lin1 hin2 lin2 lin3 hin3 fault sd brin vss com lon3 lop3 lon2 lop2 lon1 lop1 br 5.3mm 5.3mm vfh1 5.0mm mqfp64 1 64 4.5mm vfh2 vfh3 vfl1 vfl2 vfl3 dsl1 dsl2 dsl3 dsb 52 51 33 32 20 19 hoq3 hoq2 hoq1 loq1 loq2 loq3 vcc 3.5mm (4.3mm) 3.5mm (4.3mm) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 31 30 29 28 27 26 25 24 23 22 21 53 54 55 56 57 58 59 60 61 62 63
www.irf.com 17 ir2238q world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105 this product has been designed and qualified for the consumer market. qualification standards can be found on ir?s web site http://www.irf.com data and specifications subject to change without notice. 10/5/2004 ase outine 01054 00 01202 01 0222 4ead

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